1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) in which a magneto resistive effect is used.
2. Description of the Related Art
A magnetic random access memory in which a tunneling magneto resistive (TMR) effect is used is described, for example, in Non-Patent Document 1. This magnetic random access memory is characterized in that data is stored by a magnetized state of a magnetic tunnel junction (MTJ) element.
The MTJ element indicating the TMR effect has a structure in which a tunnel insulating layer is held between two ferromagnetic layers. The MTJ element is capable of taking two states, one state is a parallel state in which directions of remnant magnetization of two ferromagnetic layers holding the tunnel insulating layer therebetween are the same, and the other state is an anti-parallel state in which directions of remnant magnetization of two ferromagnetic layers holding the tunnel insulating layer therebetween are opposite to each other.
When the MTJ element is brought into the parallel state, a resistance value of the MTJ element is minimized. This state is defined as a “1” state. On the other hand, when the MTJ element is brought into the anti-parallel state, the resistance value of the MTJ element is maximized. This state is defined as a “0” state.
Additionally, as means for highly integrating memory cells, a structure is known in which an array of memory cells two-dimensionally arranged in a plane parallel to the surface of a semiconductor substrate (cell array plane) is stacked in a multiplicity of layers (see Patent Documents 1 to 8).
When this structure is used, MOS transistors have to be stacked in a dynamic random access memory (DRAM), a flash memory or the like, and therefore this structure is not suitable in a manufacturing process. This is because a high-temperature process is required for forming the MOS transistor, and this high-temperature process adversely affects characteristics of an already formed MOS transistor, wiring or the like.
On the other hand, ferromagnetic materials which do not require any high-temperature process may be stacked in a magnetic random access memory. Therefore, a structure in which memory cell arrays are stacked in a multiplicity of layers is very effective as means for highly integrating the memory cells for the magnetic random access memory in which the ferromagnetic material is used in the memory cell.
However, in structures described, for example, in Patent Documents 1 to 6, only one MTJ element is disposed in an intersecting portion of two write lines. In this structure, to electrically connect the MOS transistor as a selection switch to a plurality of MTJ elements arranged above the transistor, a region where a contact pillar is disposed is required when viewed in the cell array plane. This region cannot be overlapped with two write lines, and an area per cell increases that much more.
On the other hand, in structures described, for example, in Patent Documents 7, 8, a plurality of MTJ elements are stacked in the intersecting portion of two write lines. Therefore, the contact pillar for electrically connecting the MOS transistor to the plurality of. MTJ elements can be overlapped with one of two write lines, and the area of the cell is equal to that of the cell array of one-transistor 1MTJ type.
However, since a plurality of MTJ elements having the same shape are stacked in the same direction (easy axis directions of magnetization of storage layers are the same) in this structure, data cannot be independently written in a plurality of MTJ elements arranged in the intersecting portion of two write lines.
Patent Documents 1 to 9 and Non-Patent Document 1 are as follows:
Patent Document 1: U.S. Pat. No. 6,445,613;
Patent Document 2: Jpn. Pat. Appln. KOKAI Publication No. 2001-357666;
Patent Document 3: Jpn. Pat. Appln. KOKAI Publication No. 2002-8366;
Patent Document 4: Jpn. Pat. Appln. KOKAI Publication No. 2003-229547;
Patent Document 5: Jpn. Pat. Appln. KOKAI Publication No. 2003-249072;
Patent Document 6: Jpn. Pat. Appln. KOKAI Publication No. 2000-247093;
Patent Document 7: U.S. Pat. No. 6,169,689;
Patent Document 8: U.S. Pat. No. 5,930,164;
Patent Document 9: U.S. Pat. No. 6,545,906; and
Non-Patent Document 1: Roy Scheuerlein et al. “A 10 ns Read and Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, pp. 128–129.